GitHub

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation

QiMeng-SALV introduces a novel framework for Verilog code generation that shifts reinforcement learning optimization from module-level to signal-level rewards. By leveraging AST analysis and ...
IEEE

Generation of Synthesizable Verilog Code from Natural Language Specifications

Abstract: This study presents a method for generating synthesizable Verilog code for digital integrated circuits directly from natural-language specifications. The approach combines large language ...
IEEE

SecFSM: Knowledge Graph-Guided LLMs for Generating Secure Verilog Code of Finite State ...

Abstract: Finite State Machines (FSMs), typically implemented in Verilog, are fundamental to the control logic of Systems-on-Chip (SoCs). With recent advances in large language models (LLMs) for code ...
GitHub

svd-ai-lab/matlab-mcp-server

A Model Context Protocol (MCP) server that enables seamless integration between MATLAB and MCP-compatible applications like Claude Code. Execute MATLAB code, manage workspace variables, create plots, ...